Title :
Universal test set generation for CMOS circuits
Author :
Chen, Beyin ; Lee, Chung Len
Author_Institution :
Dept. of Electron. Eng. & Inst. of Electron., National Chiao Tung Univ., Hsin-Chu, Taiwan
Abstract :
In this paper, a fast algorithm to generate universal test set for CMOS circuits is presented. The algorithm generates the tests directly by Shannon-expanding and complementing the function, instead of the truth table enumeration. Experimental results show that this algorithm achieves an improvement of 2-6 orders of magnitude in computation efficiency and a saving of 1~2000 fold for test-storing over the method of truth table enumeration
Keywords :
CMOS integrated circuits; automatic testing; computational complexity; integrated circuit testing; integrated logic circuits; logic testing; CMOS circuits; universal test set; Benchmark testing; Circuit faults; Circuit testing; Electrical fault detection; Electronic equipment testing; Fault detection; Input variables; Logic functions; Logic testing; Timing;
Conference_Titel :
Test Symposium, 1993., Proceedings of the Second Asian
Conference_Location :
Beijing
Print_ISBN :
0-8186-3930-X
DOI :
10.1109/ATS.1993.398765
