DocumentCode :
2675024
Title :
Improving performance of NoCs by packet prioritization
Author :
Mohandesi, E. ; Mohandesi, M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Tehran, Tehran, Iran
fYear :
2011
fDate :
June 30 2011-July 1 2011
Firstpage :
1
Lastpage :
4
Abstract :
In this paper a method has been proposed to improve the performance of NoCs by prioritization of packets generated in the processing cores of the network. Packets generated from the processing cores with large amount of output network traffic get a higher priority compared to the packets generated from cores with ordinary output network traffic. When there is contention in an output port, the packets with higher priorities are sent first. We have prioritized packets in all ordinary applications in order to improve the performance of the NoC. Simulation results on different real traffic patterns show that when the traffic pattern of the NoC is not uniform, our method achieves a significant improvement in performance while adding a low area overhead to the arbiter of the network switch. In addition, to efficiently design the proposed arbiter, a model in gate level is presented.
Keywords :
logic design; network-on-chip; NoC; arbiter design; network traffic; packet prioritization; traffic pattern; Computer aided instruction; Design methodology; Pins; Round robin; Switches; Telecommunication traffic; Traffic control; Arbiter Design; NoC; Packet Prioritization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signals, Circuits and Systems (ISSCS), 2011 10th International Symposium on
Conference_Location :
lasi
Print_ISBN :
978-1-61284-944-7
Type :
conf
DOI :
10.1109/ISSCS.2011.5978669
Filename :
5978669
Link To Document :
بازگشت