DocumentCode
2676423
Title
High Speed Serial Interface & Some Key Technology Research
Author
Cheng, Wei ; Tan, Zhenhua ; Gao, Xiaoxing ; Chang, Guiran ; Wen, Jia
Author_Institution
Software Coll., Northeastern Univ., Shenyang
fYear
2008
fDate
3-5 Aug. 2008
Firstpage
562
Lastpage
566
Abstract
In a PC system, external storage interface is still a bottleneck in spite of its continuous improving performance. This makes I/O interface a bottleneck of high performance systems, especially graphics and disk storage. Increase the bandwidth of an I/O bus may be achieved by either increase bus width (e.g.16b to 32b) or by increasing operating frequency. Parallel interface is difficult to be implemented because of its nature drawback, e.g., Technologies such as embedded clock, point-to-point linkage, low voltage differential signal transmission and data encoding, enables gigabit serial bus get reliable high transfer rate at practical long distance, and become the next generation of interconnection interfaces. This paper will discuss the differences between parallel ATA protocol and serial ATA protocol, and describe the hierarchical classification of serial ATA protocol model. Last a design for a parallel/serial ATA bridge connection chip will be put forward and the test performance index for this chip is also provided.
Keywords
hard discs; memory protocols; system buses; I-O interface; data encoding; embedded clock; external storage interface; high speed serial interface; low voltage differential signal transmission; parallel interface; parallel-serial protocols; performance index; point-to-point linkage; Bandwidth; Bridge circuits; Clocks; Couplings; Encoding; Frequency; Graphics; Low voltage; Protocols; Testing; Bridge connection chip; High-speed serial interface; SerDes;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Commerce and Security, 2008 International Symposium on
Conference_Location
Guangzhou City
Print_ISBN
978-0-7695-3258-5
Type
conf
DOI
10.1109/ISECS.2008.105
Filename
4606129
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