DocumentCode :
2676517
Title :
How does resource utilization affect fault tolerance?
Author :
Scherrer, Christoph ; Steininger, Andreas
Author_Institution :
Inst. fur Mess- & Schaltungstechnik, Tech. Univ. Wien, Austria
fYear :
2000
fDate :
2000
Firstpage :
251
Lastpage :
256
Abstract :
Many fault-tolerant architectures are based on the single-fault assumption, hence accumulation of dormant faults represents a potential reliability hazard. Based on the example of the fail-silent “Time-Triggered Architecture” we study sources and effects of dormant faults. We identify software as being more prone to dormant faults than hardware. By means of modeling we reveal a high sensitivity of the MTTF to the existence of even a small amount of irregularly used resources. We propose on-line testing as a means of coping with dormant faults and sketch an appropriate test strategy
Keywords :
computer testing; fault tolerant computing; resource allocation; MTTF; dormant faults; fail-silent time-triggered architecture; fault-tolerant architectures; irregularly used resources; on-line testing; resource utilization; test strategy; Computer architecture; Control systems; Fault detection; Fault diagnosis; Fault tolerance; Hardware; Hazards; Resource management; Testing; Wheels;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2000. Proceedings. IEEE International Symposium on
Conference_Location :
Yamanashi
ISSN :
1550-5774
Print_ISBN :
0-7695-0719-0
Type :
conf
DOI :
10.1109/DFTVS.2000.887163
Filename :
887163
Link To Document :
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