Title :
The design of a RSSI for the GPS receiver
Author :
Sun, Yang ; Zhang, Xiaolin ; Xia, Wenbo
Author_Institution :
Electron. & Inf. Eng., Beihang Univ., Beijing, China
Abstract :
This paper describes CMOS circuit design techniques for a limiting amplifier and received signal strength indicator (RSSI) circuits for the GPS receiver. The circuits in limiting amplifier and RSSI are all preudo differential to minimize the requirement of the supply voltage and be prepared against device mismatch. A folded diode load and folded cascade structure gain cell is introduced for each gain cell of the amplifier. The architecture of the offset subtractor is a cross-connected source-coupled pair. Based on SMIC 0.18 μm CMOS Technology with a 1.8 V supply, the RSSI provides 55 dB of log-linear range with less than 1.5 dB error due to process variation. The overall power consumption is 3.7 mW.
Keywords :
CMOS integrated circuits; Global Positioning System; amplifiers; integrated circuit design; limiters; radio receivers; CMOS circuit design techniques; GPS receiver; RSSI design; SMIC 0.18 μm CMOS technology; cross-connected source-coupled pair; folded cascade structure gain cell; folded diode load; gain 55 dB; limiting amplifier; power 3.7 mW; received signal strength indicator circuits; voltage 1.8 V; Substrates; TV; CMOS analog integrated circuit; GPS Receiver; RSSI; limiting amplifier;
Conference_Titel :
Computer, Mechatronics, Control and Electronic Engineering (CMCE), 2010 International Conference on
Conference_Location :
Changchun
Print_ISBN :
978-1-4244-7957-3
DOI :
10.1109/CMCE.2010.5609858