Optimizing the number of channels for time interleaved sample-and-hold circuits

A technique for optimizing the number of channels for time-interleaved sample-and-hold is proposed. This technique permits to extract the figure of merit of a single sample- and-hold circuit while taking into account the limited gain- bandwidth of a family of operational amplifiers sharing the same topology. A double-sampled architecture of sample-and-holds is used to reduce die area and power consumption. The extracted results allow us to determine the optimal operation frequency and consequently the optimal number of channels for a given sampling frequency required by the time-interleaved sample-and- hold. A demonstration is shown for a gain boosted folded cascode operational amplifier topology in a 65 nm technology.