Delay and sampling-rate aware architectural synthesis in presence of communication overhead

This paper presents a technique for the minimization of the delay and sampling rate in the architectural synthesis of cyclic data flow graphs (DFGs) representing DSP algorithms taking into consideration the interconnect communication delays. In this paper, the question of optimizing the I/O delay without scarifying the iteration period (sampling rate) with non-negligible interconnects communication overhead is addressed. The proposed technique operating on the cyclic DFG of a DSP algorithm is designed to evaluate the relative firing times of the nodes by using Floyd-Warshallpsilas longest path algorithm so that the communication overhead is taken into consideration to provide an optimized time and processor schedule. Moreover, the proposed scheme is applied to well-know DSP benchmarks and the obtained synthesis results reveal that the proposed scheme is efficient in minimizing the I/O delay without scarifying the sampling rate.