A 2.8 GS/s 44.6 mW Time-Interleaved ADC Achieving 50.9 dB SNDR and 3 dB Effective Resolution Bandwidth of 1.5 GHz in 65 nm CMOS

This paper presents a power- and area-efficient 24-way time-interleaved successive-approximation-register (SAR) analog-to-digital converter (ADC) that achieves 2.8 GS/s and 8.1 ENOB in 65 nm CMOS. To minimize the power and the area, the capacitors in the capacitive DAC are sized to meet the thermal noise requirements rather than the matching requirements, leading to the LSB capacitance of 50 aF. An on-chip digital background calibration is used to calibrate the capacitor mismatches in individual ADC channels, as well as the inter-channel offset, gain and timing mismatches. Measurement results at the 2.8 GS/s sampling rate show that the ADC chip prototype consumes 44.6 mW of power from a 1.2 V supply while achieving peak SNDR of 50.9 dB and retaining SNDR higher than 48.2 dB across the entire first Nyquist zone with a $1.8{\rm V} _{{\rm pp}mathchar$ input signal. The prototype chip occupies an area of 1.03 $,\times,$ 1.66 ${\rm mm}^{2}$ , including the pads and the testing circuits. The figure of merit (FoM) of this ADC, calculated with the minimum SNDR in the first Nyquist zone, is 76 fJ/conversion-step.