Title :
Multi-loops phase locked system
Author :
Yu Zhong ; Shao Zhibiao
Author_Institution :
Inst. of Electron. Eng., Xi´an Jiaotong Univ., Shaanxi, China
Abstract :
This paper describes the design of a system used to derive high-speed time signals for SONET/SDH based equipment. This system was combined of three phase-locked loops. After optimized separately, the parameters of the loops were combined together. These three phase-locked loops share the same filter and voltage-controlled oscillator, so the size of the chip is reduced.
Keywords :
SONET; clocks; phase locked loops; synchronisation; synchronous digital hierarchy; timing circuits; SDH based equipment; SONET based equipment; high-speed time signals; multiloops phase locked system; phase-locked loops; signal filter; voltage-controlled oscillator;
Conference_Titel :
ASIC, 2003. Proceedings. 5th International Conference on
Print_ISBN :
0-7803-7889-X
DOI :
10.1109/ICASIC.2003.1277316
