DocumentCode :
2686156
Title :
Architecture for high speed evolutionary learning
Author :
Yoshikawa, Masatoshi ; Terai, Hirotaka
Author_Institution :
VLSI Center, Ritsumeikan Univ., Shiga, Japan
Volume :
2
fYear :
2003
fDate :
21-24 Oct. 2003
Firstpage :
769
Abstract :
This paper discusses the architecture for high speed learning of neural networks (NN) using genetic algorithms (GA). The proposed architecture prevents local minimum by using the GA characteristics by holding several individual populations for a population-based search and achieves high speed processing adopting dedicated hardware. To keep general purposes equal software, the proposed architecture can be flexible genetic operations on GA and introduced both Heaviside function and Sigmoid function on NN. Furthermore, the proposed architecture is proposed not only the pipeline at evaluation phase on NN, but also the pipeline on the whole at evolutionary phase on GA. Simulation results evaluating the proposed architecture are shown to achieve 750 times the speed on average compared with software processing.
Keywords :
genetic algorithms; learning (artificial intelligence); neural nets; pipeline processing; search problems; Heaviside function; Sigmoid function; dedicated hardware; flexible genetic operations; general purposes equal software; genetic algorithms; high speed evolutionary learning; individual populations; local minimum; neural networks; pipeline processing; population-based search; software processing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC, 2003. Proceedings. 5th International Conference on
ISSN :
1523-553X
Print_ISBN :
0-7803-7889-X
Type :
conf
DOI :
10.1109/ICASIC.2003.1277324
Filename :
1277324
Link To Document :
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