Title :
A TDMA/TDD processing unit IP core for WLL cell station targeting FPGA implementation
Author :
Israsena, P. ; Meenakarn, C. ; Jewajinda, Yutana ; Duangtanoo, P.
Author_Institution :
Thailand IC Design Incubator, National Electron. & Comput. Technol. Center, Bangkok, Thailand
Abstract :
This paper describes how the TDMA/TDD processing unit, which is conventionally implemented as an ASIC, can be successfully adopted using FPGA technology. The TDMA/TDD soft IP, with its internal memory requirement, is particularly suitable for FPGA implementation. The design was successfully tested at the laboratory stage as a component for a cell station of a PHS wireless system to be used in wireless local loop system as a viable alternative for rural telephone systems. The core, when implemented on a cost-effective FPGA, is able to operate at up to 30MHz.
Keywords :
application specific integrated circuits; cellular radio; field programmable gate arrays; time division multiple access; ASIC; FPGA implementation; FPGA technology; IP core; PHS wireless system; TDD processing unit; TDMA processing unit; WLL cell station; internal memory requirement; rural telephone systems; wireless local loop system;
Conference_Titel :
ASIC, 2003. Proceedings. 5th International Conference on
Print_ISBN :
0-7803-7889-X
DOI :
10.1109/ICASIC.2003.1277333