Title :
Layout optimization and modeling of an ESD-protection n-MOSFET in 0.13um silicide CMOS technology
Author :
Yuxi, Jiang ; Jiao, Li ; Feng, Ran ; Yang, Dian
Author_Institution :
Minist. of Educ. Microelectron. R&D Center, Shanghai Univ., Shanghai
Abstract :
In this paper, a lot of CMOS devices with different device dimensions, spacings, and clearances have been drawn and fabricated to find the optimized layout rules for electrostatic discharge (ESD) protection in 0.13 um Silicide CMOS Technology. The dependences of layout parameters on ESD protection ability of GGNMOS are investigated by using the TLP (transmission line pulsing) measurement technique. A DC model for modeling ESD NMOS snapback characteristics is also presented in this paper.
Keywords :
CMOS integrated circuits; MOS integrated circuits; MOSFET circuits; electrostatic discharge; integrated circuit layout; integrated circuit modelling; CMOS Technology; DC model; ESD-protection; GGNMOS; electrostatic discharge protection; n-MOSFET; size 0.13 mum; transmission line pulsing measurement technique; Breakdown voltage; CMOS technology; Design optimization; Electrostatic discharge; MOS devices; MOSFET circuits; Protection; Semiconductor device modeling; Silicides; Stress;
Conference_Titel :
Electronic Packaging Technology & High Density Packaging, 2008. ICEPT-HDP 2008. International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-2739-0
Electronic_ISBN :
978-1-4244-2740-6
DOI :
10.1109/ICEPT.2008.4607003
