Title :
A VLSI chip of SCLA based 2-D DWT/IDWT
Author :
Leibo Liu ; Ning Chen ; Hongying Meng ; Li Zhang ; Zhihua Wang ; Hongyi Chen
Author_Institution :
Inst. of Microelectron., Tsinghua Univ., Beijing, China
Abstract :
We have designed a VLSI chip of spatial combinative lifting algorithm (SCLA) based 2-D biorthogonal DWT/IDWT. This DWT/IDWT processor is implemented with 9/7, 5/3 Daubechies filters and 5-level Mallat decomposition method, which can possess 30 frames per second with image resolution up to 1280 × 1024 × 24 bits under 50 MHz system clock. This processor is fabricated with DONGBU 0.25 μm 1P4M standard CMOS technology, with 25k logic gates plus 93k bits on-chip memory and 1.1mW/MHz power consumption, in a 7.84 mm2 die size, which can be used as a compact and efficient hard IP core for JPEG2000 codec VLSI implementation and many other real-time video/audio applications.
Keywords :
CMOS integrated circuits; VLSI; codecs; discrete wavelet transforms; microprocessor chips; 0.25 microns; 1.1 mW; 50 MHz; DWT processor; Daubechies filters; IDWT processor; JPEG2000 codec; Mallat decomposition method; SCLA based 2-D DWT/IDWT; VLSI chip; audio applications; real-time video application; spatial combinative lifting algorithm;
Conference_Titel :
ASIC, 2003. Proceedings. 5th International Conference on
Print_ISBN :
0-7803-7889-X
DOI :
10.1109/ICASIC.2003.1277355