A new type of low-power adiabatic circuit with complementary pass-transistor logic

A new low-power adiabatic logic, complementary pass-transistor adiabatic logic (CPAL), is presented. The CPAL circuit uses complementary pass-transistor logic for logic-evaluation and transmission gates for energy-recovery, to realize efficient energy transfer and low energy loss. The non-adiabatic loss of output loads has been eliminated completely. An inverter chain was simulated and verified using MOSIS 0.25μm CMOS technology. Simulation results with SPICE show that the CPAL inverter chain is 2.5 to 3 times more energy efficient than 2N-2N2P and 3 to 9 times less dissipative than the static CMOS for clock rates ranging from 25 to 300MHz. In conclusion, the CPAL circuit has better energy saving advantage, and its energy dissipation is insensitive to output load capacitance and less dependency on power-clock frequency.