Parasitic-aware RF IC design

Parasitic-aware CAD synthesis techniques for RF integrated circuits based on simulated annealing with tunneling, particle swarm optimization, and non-dominated sorting genetic algorithms are presented. Computationally efficient techniques for post-optimization process, voltage, and temperature (PVT) Monte-Carlo sensitivity analysis are also described, and several design examples of RF integrated circuits in CMOS and SiGe BiCMOS technologies are shown to validate the parasitic-aware synthesis methodology.