Abstract :
A description is given of a hot-electron-effect analyzer incorporated into a critical path analysis tool, Ltime, for CMOS circuits. Using some empirical relationships, the author correlates the accumulated charge in the oxide to the size and capacitive load of the individual transistors. Effective stress time is calculated, using the time spent in the saturation region of each transistor, the results of a static switching probability analyzer, and the clock period. The methods developed can be used to predict circuit performance variation due to hot carriers as a function of time
Keywords :
CMOS integrated circuits; delays; hot carriers; probability; semiconductor device models; switching; CMOS circuit performance; Ltime; accumulated charge; capacitive load; clock period; critical path analysis tool; hot-electron-effect analyzer; oxide charge; saturation region; static switching probability analyzer; stress time; transistor delays; transition size;
