Title :
A 3.8 ns CMOS 16×16 multiplier using complementary pass transistor logic
Author :
Yano, Kazuo ; Yamanaka, Toshiaki ; Nishida, Takashi ; Saitoh, Masayoshi ; Shimohigashi, Katsuhiro ; Shimizu, Akihoro
Abstract :
A 3.8-ns, 257-mW CMOS 16×16 multiplier with a supply voltage of 4 V is described. A complementary pass transistor logic (CPL) is proposed and applied to almost the entire critical path. The CPL consists of complementary input/output, an NMOS-pass-transistor logic network, and CMOS output inverters. The CPL is twice as fast as the conventional CMOS due to lower input capacitance and greater logic construction ability. Its multiplication time is believed to be the fastest ever reported, even including times of bipolar and GaAs ICs, and it is shown to be further enhanced to 2.6 ns and 60 mW at 77 K
Keywords :
CMOS integrated circuits; digital arithmetic; digital integrated circuits; multiplying circuits; 16 bit; 2.6 ns; 257 mW; 3.8 ns; 4 V; 60 mW; 77 K; CMOS; CMOS output inverters; CPL; NMOS-pass-transistor logic; complementary input/output; complementary pass transistor logic; critical path; logic construction ability; lower input capacitance; multiplication time; supply voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 1989., Proceedings of the IEEE 1989
Conference_Location :
San Diego, CA, USA
DOI :
10.1109/CICC.1989.56843
