Investigation of charge-trap memories with AlN based band engineered storage layers

Author

Molas, G. ; Colonna, J.P. ; Kies, R. ; Belhachemi, D. ; Bocquet, M. ; Gely, M. ; Vidal, V. ; Brianceau, P. ; Vandroux, L. ; Ghibaudo, G. ; De Salvo, B.

Author_Institution

MINATEC, CEA, Grenoble, France

fYear

2010

fDate

16-19 May 2010

Firstpage

1

Lastpage

4

Abstract

This paper presents an in-depth investigation of the electrical properties of charge trap memories with AlN based storage layers. The memory performance and reliability are studied in details and compared with the ones of a reference device using standard Si₃N₄ as storage layer. An engineered charge trapping layer is also proposed, made by an AlN/Si₃N₄ double layer, which shows reduced program/erase voltages, combined with 10⁶ excellent endurance and good retention (ΔV_T>5V after 10 years at 125°C).

Keywords

III-V semiconductors; circuit reliability; semiconductor storage; wide band gap semiconductors; band engineered storage layers; charge-trap memories; electrical properties; reliability; Aluminum oxide; Atherosclerosis; Dielectric materials; Dielectric measurements; Electron traps; Material storage; Photonic band gap; Reliability engineering; Tin; Voltage; AlN; Charge trap memories; MANOS; TANOS; engineered charge trapping layer; reliability;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Workshop (IMW), 2010 IEEE International

Conference_Location

Seoul

Print_ISBN

978-1-4244-6719-8

Electronic_ISBN

978-1-4244-7668-8

Type

conf

DOI

10.1109/IMW.2010.5488309

Filename

5488309