“Nothing” can be better: Study of porosity in the charge trap layer of Flash memory

Discrete charge storage devices based on traps and nanocrystals (NCs) are shown to alleviate the problems of stress induced leakage currents (SILC) that ultimately limits the tunnel oxide scaling. Also, electric field enhancement in the tunnel oxide due to metal NCs boosts carrier injection efficiency from the channel thereby lowering program/erase voltages. This study investigates another possibility of generating such field asymmetry in the gate stack through the use of nano-porous dielectrics. The inherent difference in programming and retention mechanisms (F-N against direct tunneling) may be further widened through engineered pores. We investigate the effect of nano pores (NPs) in the charge storage layer through simulation and then present experimental results of porous TiO₂.