Title :
Allowing cycle-stealing direct memory access I/O concurrent with hard-real-time programs
Author :
Huang, Tai-Yi ; Liu, Jane W S ; Chung, Jen-Yao
Author_Institution :
Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
Abstract :
Hard-real-time schedulability analysis is carried out based on the assumption that the worst-case execution time (WCET) of each task is known. Cycle-stealing Direct Memory Access (DMA) I/O steals bus cycles from an executing program and prolongs the execution time of the program. Because of the difficulty in bounding the interference on the executing program, cycle-stealing DMA I/O is often disabled in hard-real-time systems. This paper presents an analytical method for bounding the WCET of a program executing concurrently with cycle-stealing DMA I/O. This is an extension of our previous work which bounded the WCET of a straight-line sequence of instructions when cycle-stealing operations are allowed. We demonstrate the effectiveness of our method with experiments on several programs
Keywords :
fault tolerant computing; file organisation; real-time systems; I/O concurrent; bus cycles; cycle-stealing direct memory access; cycle-stealing operations; hard-real-time programs; schedulability analysis; straight-line sequence; worst-case execution time; Assembly; Computer science; Frequency; Performance analysis; Pipelines; Processor scheduling; Programming profession; Reduced instruction set computing; Time factors; Timing;
Conference_Titel :
Parallel and Distributed Systems, 1996. Proceedings., 1996 International Conference on
Conference_Location :
Tokyo
Print_ISBN :
0-8186-7267-6
DOI :
10.1109/ICPADS.1996.517590