DocumentCode
2697040
Title
Method of deciding burn-in stress voltage in conceptual design phase
Author
Seo, Jae Yong ; Park, Noh Seok ; Park, Hyung-Jin ; Park, Hong Sik ; Kim, Woo Sup ; Lim, Se Young ; Kim, Hyun ; Cha, Nam Hyun ; Kang, Ju Seong ; So, Byung Se
Author_Institution
Memory Div., Samsung Electron., Hwasung, South Korea
fYear
2010
fDate
2-6 May 2010
Firstpage
1004
Lastpage
1005
Abstract
Design for next generation DRAM on early development stage should be concerned about the intrinsic reliability margins and maximum Burn-in stress voltage. This paper proposes that BI stress voltage, when latent defects could not be evaluated by burn-in to obtain the acceleration parameters, is decided by the increasing ratio of historical burn-in stress voltage trend.
Keywords
DRAM chips; integrated circuit design; integrated circuit reliability; BI stress voltage; acceleration parameters; intrinsic reliability margins; maximum burn-in stress voltage method; next generation DRAM design; Acceleration; Bismuth; Circuits; Equations; Etching; History; Monitoring; Random access memory; Stress; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability Physics Symposium (IRPS), 2010 IEEE International
Conference_Location
Anaheim, CA
ISSN
1541-7026
Print_ISBN
978-1-4244-5430-3
Type
conf
DOI
10.1109/IRPS.2010.5488686
Filename
5488686
Link To Document