Title :
Role of interface layer in stress-induced leakage current in high-k/metal-gate dielectric stacks
Author :
Chang, W.L. ; Stathis, J.H. ; Cartier, E.
Author_Institution :
Microelectron. Div., IBM, Hopewell Junction, NY, USA
Abstract :
The impact of the Silica-based interface layer (IL) thickness on stress induced leakage current (SILC) on high-k/metal-gate transistors is studied at various constant voltage stresses (CVS) and at various temperatures. It is shown that high-k/metal-gate transistors reliability can be greatly improved with interface layer optimization.
Keywords :
field effect transistors; leakage currents; optimisation; semiconductor device reliability; silicon compounds; CVS; FET; SILC; SiO2; constant voltage stress; high-k/metal-gate dielectric stacks; high-k/metal-gate transistors reliability; silica-based interface layer optimisation; stress induced leakage current; Breakdown voltage; Electric breakdown; Fluctuations; Gate leakage; High K dielectric materials; High-K gate dielectrics; Leakage current; Low voltage; Stress; Temperature; SILC; TDDB; component; high-k dielectrics;
Conference_Titel :
Reliability Physics Symposium (IRPS), 2010 IEEE International
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4244-5430-3
DOI :
10.1109/IRPS.2010.5488732
