Title :
Interconnect noise analysis for megabit DRAMs
Author :
Yuan, J.S. ; Liou, J.J.
Author_Institution :
Univ. of Central Florida, Orlando, FL, USA
Abstract :
Analytical noise modeling of the bit line coupling analysis for various DRAM architectures has been developed. Intrabit and interbit line coupling for true folded, interdigitated, and twisted architectures are analyzed. Analytical equations for the noise-to-signal ratio are derived based on the charge conservation and the current continuity equations. The time-dependent differential equations for twisted architectures are presented. The analytical expressions provide insight into the charge redistribution when the word lines turn on. The topology for array noise extraction in SPICE circuit simulation is presented. SPICE simulations are found to be in good agreement with the analytical results
Keywords :
DRAM chips; circuit CAD; digital simulation; electron device noise; memory architecture; DRAM architectures; SPICE circuit simulation; array noise extraction; bit line coupling analysis; charge conservation; charge redistribution; current continuity equations; folded architectures; interbit line coupling; interdigitated architectures; intrabit line coupling; megabit DRAMs; noise modeling; noise-to-signal ratio; twisted architectures; Analytical models; Capacitance; Circuit noise; Circuit simulation; Coupling circuits; Differential equations; Random access memory; SPICE; Switches; Voltage;
Conference_Titel :
VLSI Multilevel Interconnection Conference, 1990. Proceedings., Seventh International IEEE
Conference_Location :
Santa Clara, CA
DOI :
10.1109/VMIC.1990.127867
