Title :
A simple electrical method for etch bias and process reliability determination
Author :
Yiang, Kok-Yong ; Chin, Melida ; Marathe, Amit ; Aubel, Oliver
Author_Institution :
Technol. Reliability Dev., GLOBALFOUNDRIES Inc., Sunnyvale, CA, USA
Abstract :
A fast and simple electrical method is developed to characterize the etch bias and post-patterned ILD breakdown strength of back-end-of-line (BEOL) interconnects, as well as the middle-of-line (MOL) contact/poly module. The method provides a timely and valuable monitoring mechanism for assessing lithography, etch, thin-film quality and process reliability windows.
Keywords :
CMOS integrated circuits; electric breakdown; etching; integrated circuit interconnections; integrated circuit reliability; lithography; CMOS technology; back-end-of-line interconnects; etch bias electrical method; intralevel dielectric breakdown; lithography; middle-of-line contact-poly module; post-patterned ILD breakdown strength; process reliability determination; process reliability windows; thin-film quality; CMOS technology; Chemical technology; Dielectric breakdown; Electric breakdown; Etching; Lithography; Monitoring; Reliability engineering; Samarium; Testing; Etch bias; VRDB; line-edge roughness (LER);
Conference_Titel :
Reliability Physics Symposium (IRPS), 2010 IEEE International
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4244-5430-3
DOI :
10.1109/IRPS.2010.5488771
