A 2 GHz, 6 mW BiCMOS frequency synthesizer

Author

Aytur, T. ; Razavi, B.

Author_Institution

AT&T Bell Labs., Holmdel, NJ, USA

fYear

1995

fDate

15-17 Feb. 1995

Firstpage

264

Lastpage

265

Abstract

This paper describes the design of an essential building block in wireless transceivers, the frequency synthesizer. The circuit operates at 2 GHz from a 3 V supply, and is fully integrated with the exception of a loop filter capacitor. Low-power and differential circuit techniques implemented in a 20 GHz BiCMOS process allow the synthesizer to consume 6 mW. A pulse-swallow architecture is adopted for the synthesizer. It consists of a mixer, a low-pass filter (LPF), a voltage-controlled oscillator (VCO), a 16/17 prescaler, a 9 b program counter, and a 7 b swallow counter.

Keywords

BiCMOS integrated circuits; UHF integrated circuits; frequency synthesizers; mixed analogue-digital integrated circuits; transceivers; 2 GHz; 20 GHz; 3 V; 6 mW; BiCMOS frequency synthesizer; UHF IC; VCO; differential circuit techniques; low-power operation; prescaler; program counter; pulse-swallow architecture; swallow counter; voltage-controlled oscillator; wireless transceivers; BiCMOS integrated circuits; Capacitance; Circuit noise; Clocks; Counting circuits; Energy consumption; Frequency conversion; Frequency synthesizers; Latches; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-2495-1

Type

conf

DOI

10.1109/ISSCC.1995.535549

Filename

535549