DocumentCode :
2704386
Title :
Low stress oxide/nitride passivation topography and influence on electrical devices
Author :
Menz, K.-D. ; Braun, R. ; Henkel, W. ; Huber, R. ; Neureither, B. ; Spindler, O. ; Treichel, H.
Author_Institution :
Siemens AG, Munich, West Germany
fYear :
1990
fDate :
12-13 Jun 1990
Firstpage :
384
Lastpage :
386
Abstract :
A new low-stress oxide/nitride sandwich passivation using layers of plasma-enhanced chemical vapor deposition (PECVD) TEOS and PECVD Si xNyHz that achieves high device lifetimes is presented. A nonplanarized low-stress sandwich as well as a planarized one are investigated. The planarization includes deposition and in-situ etching of the TEOS-based PECVD oxide. Scanning electron microscopy (SEM) analysis of narrow metal 2 spaces and via holes show a conformal oxide/nitride deposition and local planarization of the oxide without voids, respectively. In the case of the nonplanarized passivation variation, as compared to the passivation sandwich with high stress, the lifetimes of three different NMOS devices are increased by a factor of 3-4
Keywords :
integrated circuit technology; passivation; plasma CVD coatings; surface topography; NMOS devices; SEM analysis; SixNyHz; TEOS-based PECVD oxide; low-stress oxide/nitride sandwich passivation; passivation topography; planarization; plasma-enhanced chemical vapor deposition; Chemical vapor deposition; Etching; Passivation; Planarization; Plasma applications; Plasma chemistry; Plasma devices; Scanning electron microscopy; Stress; Surfaces;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Multilevel Interconnection Conference, 1990. Proceedings., Seventh International IEEE
Conference_Location :
Santa Clara, CA
Type :
conf
DOI :
10.1109/VMIC.1990.127906
Filename :
127906
Link To Document :
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