Low power design of the next-generation High Efficiency Video Coding

Author

Shafique, Muhammad ; Henkel, JoÌˆrg

Author_Institution

Dept. of Embedded Syst., Karlsruhe Inst. of Technol. (KIT), Karlsruhe, Germany

fYear

2014

fDate

20-23 Jan. 2014

Firstpage

274

Lastpage

281

Abstract

This paper provides a comprehensive analysis of the computational complexity, power consumption, temperature, and memory access behavior for the next-generation High Efficiency Video Coding (HEVC) standard. We highlight the associated design challenges and present several low-power algorithmic and architectural techniques for developing power-efficient HEVC-based multimedia system. We explore the interplay between the algorithms and architectures to provide high power efficiency while leveraging the application-specific knowledge and video content characteristics.

Keywords

multimedia communication; video coding; application-specific knowledge; computational complexity analysis; low power design; low-power algorithmic technique; low-power architectural technique; memory access behavior; next-generation high efficiency video coding standard; power consumption; power-efficient HEVC-based multimedia system; temperature; video content characteristics; Encoding; Hardware; Interpolation; Memory management; Tiles; Video coding; Video sequences; HEVC; algorithm; analysis; architecture; energy efficiency; hardware accelerator; low power design; power management; video coding; video memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific

Conference_Location

Singapore

Type

conf

DOI

10.1109/ASPDAC.2014.6742902

Filename

6742902