DocumentCode
2705652
Title
A low-voltage triggering SCR for on-chip ESD protection at output and input pads
Author
Chatterjee, A. ; Polgreen, T.
fYear
1990
fDate
4-7 June 1990
Firstpage
75
Lastpage
76
Abstract
A novel silicon-controlled rectifier (SCR) structure for on-chip protection against electrostatic discharge (ESD) stress at output or input pads is presented. The SCR switches to an ON state at a trigger voltage determined by the gate length of an incorporated nMOS-like structure. Thus the SCR can be designed to consistently trigger at a voltage low enough to protect nMOS transistors from ESD. The capability of protection circuits using the new SCR design is experimentally demonstrated. The tunability of the SCR trigger voltage with reference to the nMOS breakdown voltage is successfully exploited to improve the human-body-model ESD failure threshold of an output buffer from 1500 V to 5000 V
Keywords
electrostatic discharge; insulated gate field effect transistors; protection; thyristors; gate length; human-body-model ESD failure threshold; incorporated nMOS-like structure; input pads; low-voltage triggering SCR; on-chip ESD protection; output buffer; protection circuits; silicon-controlled rectifier; trigger voltage; tunability;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 1990. Digest of Technical Papers.1990 Symposium on
Conference_Location
Honolulu, Hawaii, USA
Type
conf
DOI
10.1109/VLSIT.1990.111015
Filename
5727475
Link To Document