Title :
A 1GB/S SCI link in 0.8/spl mu/m BiCMOS
Author :
Cecchi, D.R. ; Dina, M. ; Preuss, C.W.
Author_Institution :
Div. of Syst. Technol. & Archit., IBM Corp., Rochester, MN, USA
Abstract :
It has become increasingly evident that the performance demands of modern microprocessors are rapidly outstripping the capability of traditional multidrop busses to support the necessary data bandwidth, especially in symmetric multi-processor (SMP) configurations. The definition of a replacement for the traditional bus with a packetized network based on unidirectional point-to-point links was undertaken under the auspices of the IEEE Microprocessor Standards Committee, resulting in the IEEE 1596-1992 Scalable Coherent Interface Standard (SCI). This chip is a prototype fabricated to evaluate the feasibility of implementing a full-speed SCI link in standard 0.8/spl mu/m BiCMOS.
Keywords :
BiCMOS digital integrated circuits; microprocessor chips; system buses; 0.8 micron; 1 GB/s; BiCMOS chip; IEEE 1596-1992 Scalable Coherent Interface Standard; IEEE Microprocessor Standards Committee; SCI link; microprocessor; multidrop bus; packetized network; symmetric multi-processor; unidirectional point-to-point link; BiCMOS integrated circuits; Cables; Circuit testing; Clocks; Delay lines; Microprocessors; Packaging; Performance evaluation; Registers; System testing;
Conference_Titel :
Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-2495-1
DOI :
10.1109/ISSCC.1995.535574
