Circuit implementation of SVM training

A central issue in computational intelligence is the training phase of a learning machine. In classification problems, in particular, Support Vector Machines are one of the most effective tools. In this work an analog low-complexity circuital implementation is proposed to address the learning stage of SVMs. The circuit is a co-content minimization network based on a suitable SVM formulation embedding bias removal. Moreover the circuit complexity (i.e. the density of the kernel matrix) is effectively controlled by resorting to a proper kernel function. Experimental evidence shows the effectiveness of the proposed approach.