Title :
100 MHz serial access architecture for 4 Mb field memory
Author :
Ikeda, Hinata ; Tsujimoto, Akira ; Sato, Yoshinori ; Tajima, Junji ; Adachi, Takao ; Hamaguchi, Kunihiko ; Fukuhara, Naohiro ; Miyauchi, Mayu
Abstract :
An architecture that improves serial I/O operation speed, reduces layout area, and permits simple control is presented. The architecture features a high-speed, simple configuration, an easy controllable data shifter, and an high-speed redundancy circuit. With this architecture, a 4-Mb field memory with 100-MHz serial access capability has been developed. The process technology used is 1.0 μm CMOS, and the die size is 12.94 mm×25.9 mm. The data register circuit area of the prototype chip was 40% smaller than that of conventional chips
Keywords :
CMOS integrated circuits; DRAM chips; VLSI; integrated circuit technology; integrated memory circuits; 1 micron; 100 MHz; 100 MHz serial access architecture; 12.94 mm; 25.9 mm; 4 Mb field memory; 4 Mbit; CMOS; ULSI; data register circuit area; die size; easy controllable data shifter; high-speed; high-speed redundancy circuit; prototype chip; reduces layout area; serial I/O operation speed; simple configuration; simple control;
Conference_Titel :
VLSI Circuits, 1990. Digest of Technical Papers., 1990 Symposium on
Conference_Location :
Honolulu, Hawaii, USA
DOI :
10.1109/VLSIC.1990.111073
