Title :
A 6.8 ns 1 Mb ECL I/O BiCMOS configurable SRAM
Author :
Kertis, Bob ; Costakis, George ; Jensen, John ; Zeiter, John ; Rickard, Joan ; Pusztai, Mary ; Bowman, Terry
Abstract :
A 1-Mb ECL (emitter coupled logic) I/O SRAM which has been fabricated using 0.8-μm BiCMOS technology is described. The die is configurable to four different organizations (1 Mb×1, 1 Mb×1 with differential output, 512 K×2 with differential output, and 256 K×4) by way of bonding options. The device, with a die size of 240 mil×475 mil, has a typical access time of 6.8 ns and is 10 K or 100 K I/O compatible with a metal option
Keywords :
BIMOS integrated circuits; SRAM chips; VLSI; emitter-coupled logic; integrated circuit technology; integrated memory circuits; 0.8 micron; 1 Mbit; 10 K I/O compatible; 100 K I/O compatible; 240 mil; 475 mil; 6.8 ns; BiCMOS; ECL I/O; ECL compatible; ULSI; access time; bonding options; configurable SRAM; die size; differential output; emitter coupled logic; four different organizations; metal option; organisation 1 Mbit×1; organisation 256 K×4; organisation 512 K×2;
Conference_Titel :
VLSI Circuits, 1990. Digest of Technical Papers., 1990 Symposium on
Conference_Location :
Honolulu, Hawaii, USA
DOI :
10.1109/VLSIC.1990.111084
