DocumentCode
2706576
Title
Fast-access BiCMOS SRAM architecture with a VSS generator
Author
Douseki, Takakuni ; Ohmori, Yasuo ; Yoshino, Hideo ; Yamada, Junzo
fYear
1990
fDate
7-9 June 1990
Firstpage
45
Lastpage
46
Abstract
A fast-access intermediate supply voltage level BiCMOS SRAM (ISVOL) architecture is proposed for advancing circuit technology to megabit-level SRAMs using low-submicron MOSFETs. To verify this concept´s effectiveness, a 256-kb SRAM, with a typical access time of 5 ns, is evaluated and reported. The access time dependence of the supply voltage is shown. This architecture can suppress the access time variance to within 4% for a 15% supply voltage variation
Keywords
BIMOS integrated circuits; SRAM chips; VLSI; integrated circuit technology; integrated memory circuits; 256 kbit; 256-kb SRAM; 5 ns; BiCMOS SRAM; VLSI; VSS generator; access time; access time dependence; intermediate supply voltage level; low-submicron MOSFETs; megabit-level SRAMs; supply voltage variation;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 1990. Digest of Technical Papers., 1990 Symposium on
Conference_Location
Honolulu, Hawaii, USA
Type
conf
DOI
10.1109/VLSIC.1990.111087
Filename
5727520
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