Title :
A 10-bit binary-weighted DAC with digital background LMS calibration
Author :
Shen, Ding-Lan ; Lai, Yuan-Chun ; Lee, Tai-Cheng
Author_Institution :
Nat. Taiwan Univ., Taipei
Abstract :
A 10-bit binary-weighted DAC utilizes identical transistors with different overdrive voltages to achieve small area and high speed. Employing LMS calibration, the proposed current-steering DAC can be digitally calibrated in the background. The measured SFDR of the output signal at 61 kHz can be improved by 19 dB at 1 GS/s. The 10-bit DAC occupies 0.2 mm2 in a 0.18-mum CMOS technology and consumes 27 mW from a 1.8-V supply.
Keywords :
CMOS integrated circuits; digital-analogue conversion; CMOS technology; SFDR; binary-weighted DAC; current-steering DAC; digital background LMS calibration; frequency 61 kHz; power 27 mW; size 0.18 mum; voltage 1.8 V; CMOS technology; Calibration; Costs; Decoding; Ethernet networks; HDTV; Least squares approximation; Solid state circuits; Transistors; Voltage; LMS calibration; binary-weighted DAC;
Conference_Titel :
Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian
Conference_Location :
Jeju
Print_ISBN :
978-1-4244-1359-1
Electronic_ISBN :
978-1-4244-1360-7
DOI :
10.1109/ASSCC.2007.4425703
