Title :
A New Generalized Reconfigurable Architecture for Digital Signal Processor
Author :
Basu, Joyanta ; Sahidullah, Md ; Sinha, Amitabha
Author_Institution :
West Bengal Univ. of Technol., Kolkata
Abstract :
In this paper a novel re-configurable digital signal processing (DSP) architecture and algorithm has been proposed where basic building blocks are high performance adders, subtracters, multipliers etc. The architecture has been conceived keeping high performance, low dynamic configuration latency, flexibility and low power consumption in view. Issues involving interconnection among the basic building blocks have been dealt with in details and a new scheme is proposed.
Keywords :
digital signal processing chips; integrated circuit interconnections; low-power electronics; reconfigurable architectures; digital signal processor; dynamic configuration latency; generalized reconfigurable architecture; power consumption; Adders; Application software; Computer architecture; Digital signal processing; Digital signal processors; Discrete Fourier transforms; Finite impulse response filter; IIR filters; Reconfigurable architectures; Signal processing algorithms;
Conference_Titel :
Advanced Computing and Communications, 2007. ADCOM 2007. International Conference on
Conference_Location :
Guwahati, Assam
Print_ISBN :
0-7695-3059-1
DOI :
10.1109/ADCOM.2007.108
