DocumentCode :
2711868
Title :
A test chip for interconnect capacitance modelling in a CMOS process
Author :
Nouet, Pascal ; Toulouse, Alain
Author_Institution :
LIRMM, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
fYear :
1996
fDate :
25-28 Mar 1996
Firstpage :
61
Lastpage :
65
Abstract :
Based on our previous works on On-Chip measurement of small capacitances, we present a Test Chip to provide experimental data for measurement and modelling of wiring capacitances of a CMOS Process. Patterns include line-to-line capacitance (for the two metal layers and the polysilicon layer), inter-layer capacitance (extraction of both area and perimeter terms of the capacitance for each couple of layer), matching (relative scattering between two identical devices), crossover (capacitance between two crossing lines) and other parameters generally used when extracting parasitic elements from an electronic design
Keywords :
CMOS integrated circuits; capacitance measurement; integrated circuit interconnections; integrated circuit modelling; integrated circuit testing; CMOS process; crossover; electronic design; inter-layer capacitance; interconnect capacitance modelling; line-to-line capacitance; matching; metal layer; on-chip measurement; parasitic elements; polysilicon layer; scattering; test chip; wiring capacitance; CMOS process; Capacitance measurement; Data mining; Parasitic capacitance; Pattern matching; Scattering parameters; Semiconductor device measurement; Semiconductor device modeling; Testing; Wiring;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronic Test Structures, 1996. ICMTS 1996. Proceedings. 1996 IEEE International Conference on
Conference_Location :
Trento
Print_ISBN :
0-7803-2783-7
Type :
conf
DOI :
10.1109/ICMTS.1996.535622
Filename :
535622
Link To Document :
بازگشت