Hardware implementation of Spiking Neural Network classifiers based on backpropagation-based learning algorithms

Spiking Neural Networks (SNNs) have become an important research theme due to new discoveries and advances in neurophysiology, which states that information among neurons is interchanged via pulses or spikes. FPGAs are widely used for implementing high performance digital hardware systems, due to its flexibility and because they are suitable for the implementation of systems with high degree of parallelism. FPGAs have become an important tool because fine grain digital elements useful for efficient hardware implementation of SNNs are provided, making FPGA device suitable for implementing SNNs. Several attempts for implementing efficient classifiers in hardware have been done, but most of them fail because the processing elements are costly in terms of hardware resource utilization. SNNs are less hardware greedy, and the nature of the pulsed processing is well suited to the digital processing blocks of the FPGA devices. In this work, a hardware architecture for implementing both recall and learning phases required for Multilayer FeedForward SNNs is proposed. Results and performance statics are provided.