A 20 Gb/s Clock and Data Recovery With a Ping-Pong Delay Line for Unlimited Phase Shifting in 65 nm CMOS Process

This paper describes a 20 Gb/s receiver with a DLL-based CDR, which uses a proposed Ping-Pong delay line (PPDL) in order to ameliorate the limited operating range problem of the DLL. The unlimited phase shifting algorithm with the PPDL extends the tracking range of the DLL-based CDR. The PPDL correlates two variable delay lines and swaps each other whenever one of them reaches its operational limit. The chip occupies 0.24 mm² in 65 nm CMOS process. The power efficiency of the data transfer is 8.46 mW/Gb/s. The measured jitter of the 5 GHz clock is 1.125 ps_rms and the data eye opening is 0.613UI.