Title :
A Built-In Characterization Technique for 1-Bit/Stage Pipelined ADC
Author :
Chou, Y.-H. ; Huang, J.-L. ; Huang, X.-L.
Abstract :
In this paper, we present, for the 1-bit/stage pipelined ADC, a self-characterization technique that quantifies the per-stage capacitor ratio and comparator offset - the two main nonlinearity sources. In the proposed loop test, two adjacent pipelined stages are reconfigured to form a loop. Then, DC test stimuli are applied. The capacitor ratio and comparator offset of the stage under test are derived from the recorded output sequences. Numerical simulations are performed to validate the proposed technique.
Keywords :
analogue-digital conversion; comparators (circuits); numerical analysis; DC test stimuli; adjacent pipelined stage; built-in characterization technique; comparator offset; loop test; nonlinearity source; numerical simulation; per stage capacitor ratio; pipelined ADC; self characterization technique; Calibration; Capacitors; Clocks; Estimation error; Numerical simulation; Testing; design-for-test; mixed-signal; pipelined ADC;
Conference_Titel :
Test Symposium (ATS), 2012 IEEE 21st Asian
Conference_Location :
Niigata
Print_ISBN :
978-1-4673-4555-2
Electronic_ISBN :
1081-7735
DOI :
10.1109/ATS.2012.21
