DocumentCode :
2715046
Title :
A two-dimensional logarithmic number system (2DLNS)-based Finite Impulse Response (FIR) filter design
Author :
Azarmehr, Mahzad ; Ahmadi, Majid ; Jullien, Graham A.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Windsor, Windsor, ON, Canada
fYear :
2011
fDate :
26-29 June 2011
Firstpage :
37
Lastpage :
40
Abstract :
The ever increasing demand for low power DSP applications has directed researchers to contemplate a variety of potential approaches in different contexts. In this regard, using some alternative number systems, which inherently are capable of reducing the hardware complexity, have been propounded. In this work, a 2DLNS-based platform for multiplication intensive DSP applications is presented. Implementing an FIR filter structure on this basis shows outstanding privilege to its binary counterpart in terms of VLSI area and power consumption.
Keywords :
FIR filters; VLSI; computational complexity; power consumption; VLSI area; finite impulse response filter design; hardware complexity; low power DSP applications; power consumption; two dimensional logarithmic number system; Chirp; Clocks; Computer architecture; Digital signal processing; Finite impulse response filter; Hardware; Registers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
New Circuits and Systems Conference (NEWCAS), 2011 IEEE 9th International
Conference_Location :
Bordeaux
Print_ISBN :
978-1-61284-135-9
Type :
conf
DOI :
10.1109/NEWCAS.2011.5981213
Filename :
5981213
Link To Document :
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