DocumentCode :
2716290
Title :
Neural network VLSI of pulse operation for reduced power consumption
Author :
Han, I.S.
Author_Institution :
Korea Telecom Res. Labs., South Korea
fYear :
1995
fDate :
34852
Firstpage :
42552
Lastpage :
42555
Abstract :
The neural network application specific VLSI has been preferred in respect of its relatively fast speed, huge network size and effective cost in implementation. Broad ranges of neural network VLSI have been developed for the purpose of implementing the neural network of massive parallel operation. Among those implementations, the principle of pulse-stream operation has made a substantial improvement in speed or size with analog-digital mixed VLSIs. In this work, a way of reducing the power consumption is suggested, which is based on both the synapse circuit using analog MOSFET resistances and the pulse operation principle
Keywords :
MOS integrated circuits; VLSI; integrated circuit design; mixed analogue-digital integrated circuits; neural chips; analog MOSFET resistances; analog-digital mixed VLSI; application specific VLSI; massive parallel operation; network size; neural network VLSI; power consumption; pulse-stream operation; synapse circuit;
fLanguage :
English
Publisher :
iet
Conference_Titel :
Low Power Analogue and Digital VLSI: ASICS, Techniques and Applications, IEE Colloquium on
Conference_Location :
London
Type :
conf
DOI :
10.1049/ic:19950794
Filename :
478154
Link To Document :
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