Title :
A test structure for the measurement of planarisation
Author :
Elliott, J.P. ; Fallon, M. ; Walton, A.J. ; Stevenson, J.T.M. ; O´Hara, A.
Author_Institution :
Dept. of Electr. Eng., Edinburgh Univ., UK
Abstract :
This paper presents simulations of a test structure that can be used to assess the degree of planarisation of inter-layer dielectrics. It consists of sets of comb structures separated by a dielectric. For each structure the combs on the two layers overlap each other with adjacent structures having the overlap in one direction progressionally offset by 0.2 μm. The capacitance of these structures is then measured from which the degree of planarisation can be assessed. This structure has potential applications for characterising Chemical Mechanical Polishing (CMP) processes for multi-level VLSI applications
Keywords :
VLSI; capacitance measurement; integrated circuit interconnections; integrated circuit testing; polishing; surface treatment; capacitance measurement; chemical mechanical polishing; comb structure; inter-layer dielectric; multi-level VLSI; planarisation; simulation; test structure; Chemical technology; Dielectric measurements; Electric variables measurement; Integrated circuit interconnections; Parasitic capacitance; Planarization; Semiconductor device modeling; Surface topography; Teeth; Testing;
Conference_Titel :
Microelectronic Test Structures, 1996. ICMTS 1996. Proceedings. 1996 IEEE International Conference on
Conference_Location :
Trento
Print_ISBN :
0-7803-2783-7
DOI :
10.1109/ICMTS.1996.535664
