Dynamic parallel reconfiguration for self-adaptive hardware architectures

Adaptive Hardware Systems can rely on software or hardware adaptation. Software adaptation can be globally assimilated to mode switching, either at a technological or hardware level (DVFS, Idle processor mode ...), or at the application level (bandwidth adaptation in telecommunication, multispectral cameras, ...). Hardware adaptation corresponds to a deeper change in the internal organization of the computing architecture of an embedded system. It enables more powerful adaptation but is currently limited by the reconfiguration (tool and architecture) of today´s FPGA devices. We present in this paper a multi-FPGA platform designed to exhibit unique computing capabilities. The joint design of the electronic board and the internal architecture of each reconfigurable device permits dynamic parallel (and not partial) reconfiguration of several parts of the system while maintaining global routing and local computation in the rest of the system. Dynamic parallel reconfiguration and technological independence are enabled by considering reconfiguration at coarse grain. We describe in the paper the hardware elements composing the platform. The specific design of the global system allowed us to reach a fully operational platform. We present statistical experiments to evaluate the inter-chip network capacity which show that our platform supports up to 18 parallel reconfigurations per second.