An approach for power and performance evaluation of reconfigurable SoC at mixed abstraction levels

This work presents an analysis environment for power and performance estimation of Reconfigurable SoCs, modelled at mixed abstraction level. A monitoring strategy is integrated, that uses back-annotation of power characteristics to allow system power analysis in a SystemC simulator. A post simulation analysis tool, which contains technology dependent libraries, has been implemented to evaluate SystemC simulation results. As a case study, Ogg Vorbis was implemented on SystemC and VHDL and configured in a VirtexII Pro XC2VP30 FPGA. Results demonstrate that SystemC simulations run 28 times faster than its VHDL counterpart though providing cycle accurate modules and a high data dependent power estimation accuracy.