DocumentCode :
2722074
Title :
Copper pillar bumped sapphire flip chip on lead-frame package development
Author :
Yang, J.Z.
Author_Institution :
Peregrine Semicond., San Diego, CA, USA
fYear :
2012
fDate :
May 29 2012-June 1 2012
Firstpage :
457
Lastpage :
464
Abstract :
In the development of copper pillar bumped sapphire flip chip on lead-frame package (FCOLF), the die was found very vulnerable in assembly process. In the package reliability test the bump connection opened on the die side where the failure was initiated with cracks on die re-passivation layer. In order to find the root cause, comprehensive investigations have been carried out on wafer bumping quality check, bump and package structure finite element analysis as well as assembly process test etc. The results of the analysis & experiment as well as the process solution for volume production are presented in this paper.
Keywords :
assembling; copper; finite element analysis; flip-chip devices; sapphire; Cu; assembly process test; bump connection; copper pillar bumped sapphire flip chip; die re-passivation layer; die side; finite element analysis; lead-frame package development; package reliability test; package structure; process solution; volume production x; wafer bumping quality check; Assembly; Flip chip; Lead; Reliability; Residual stresses;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd
Conference_Location :
San Diego, CA
ISSN :
0569-5503
Print_ISBN :
978-1-4673-1966-9
Electronic_ISBN :
0569-5503
Type :
conf
DOI :
10.1109/ECTC.2012.6248871
Filename :
6248871
Link To Document :
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