Title :
Trench DRAM Technologies for the 50nm Node and Beyond
Author :
Mueller, W. ; Aichmayr, G. ; Bergner, W. ; Goldbach, M. ; Hecht, T. ; Kudelka, S. ; Lau, F. ; Nuetzel, J. ; Orth, A. ; Schloesser, T. ; Scholz, A. ; Sieck, A. ; Spitzer, A. ; Strasser, M. ; Wand, P.-F. ; Wege, S. ; Weis, R.
Author_Institution :
Infineon Technol., Dresden
Abstract :
This paper reviews the DRAM technology challenges for overcoming the 50nm barrier. First the product requirements and barriers to shrink the DRAM cell beyond 50nm will be addressed. Then the technology solutions for DRAM cell capacitor, cell transistor, and support transistors are presented. Key enablers arc high aspect ratio cell capacitor structures, new capacitor materials, 3-dimensional cell transistor schemes and high performance LSTP support device technologies
Keywords :
DRAM chips; capacitors; integrated circuit design; 3D cell transistors; 50 nm; DRAM cell capacitors; LSTP support device technologies; support transistors; trench DRAM technologies; Capacitors; Etching; FinFETs; High K dielectric materials; Material storage; Random access memory; Timing; Tin; Transistors; Voltage;
Conference_Titel :
VLSI Technology, Systems, and Applications, 2006 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
1-4244-0181-4
Electronic_ISBN :
1524-766X
DOI :
10.1109/VTSA.2006.251081
