DocumentCode :
2722544
Title :
Mapping of partial reconfigurable data flows to Xilinx FPGAs
Author :
Athalye, Akshay ; Hong, Sangjin
Author_Institution :
Stony Brook Univ., NY
fYear :
2005
fDate :
19-23 Sept. 2005
Firstpage :
111
Lastpage :
112
Abstract :
Recently, commercially available Xilinx FPGAs have started to support partial run time reconfiguration (RTR) wherein part of the FPGA can be reconfigured while the rest of the FPGA logic is functioning. However, access to the FPGA for RTR is not completely flexible and needs a systematic partitioning of the FPGA fabric into static and reconfigurable partitions within certain pretty tight constraints. Modules mapped to different partitions need to communicate using specialized macros. In this paper, we present a method for mapping a data flow requiring partial RTR to the Xilinx FPGAs. We develop a cost function that guides the mapping of nodes to these partitions by attempting to minimize the communication cost while ensuring that the required RTR is completed within certain time constraints
Keywords :
data flow graphs; embedded systems; field programmable gate arrays; logic design; reconfigurable architectures; FPGA logic; Xilinx FPGA; data flow mapping; field programmable gate arrays; partial reconfigurable data flows; partial run time reconfiguration; Adaptive signal processing; Circuits; Cost function; Fabrics; Field programmable gate arrays; Flow graphs; Hardware; Reconfigurable logic; Routing; Time factors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SOC Conference, 2005. Proceedings. IEEE International
Conference_Location :
Herndon, VA
Print_ISBN :
0-7803-9264-7
Type :
conf
DOI :
10.1109/SOCC.2005.1554473
Filename :
1554473
Link To Document :
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