Title :
Design of scan-testable CMOS sequential circuits
Author :
Park, Bong-Hee ; Menon, Premachandran R.
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusett Univ., Amherst, MA, USA
Abstract :
It is shown that the detectability of stuck-open faults in CMOS sequential circuits with scan paths containing ordinary shift register latches depends on the state assignment used. A method by which any state table can be realized by a circuit that is scan testable for stuck-open faults is presented. Tests can be applied to these circuits by shifting in only one vector per test, reducing the test application time. The proposed method is applied to five state tables from the MCNC Logic Synthesis and Optimization Benchmarks. It is found that the overhead of the method is in the range of 14% to 29%
Keywords :
CMOS integrated circuits; VLSI; integrated circuit testing; integrated logic circuits; logic design; logic testing; sequential circuits; MCNC Logic Synthesis and Optimization Benchmarks; partition theory; scan paths; scan-testable CMOS sequential circuits; shift register latches; state assignment; stuck-open faults; Circuit faults; Circuit synthesis; Circuit testing; Electrical fault detection; Fault detection; Latches; Logic; Optimization methods; Sequential circuits; Shift registers;
Conference_Titel :
Test Conference, 1990. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-8186-9064-X
DOI :
10.1109/TEST.1990.114044
