Single-fault fault collapsing analysis in sequential logic circuits

Author

Chen, Jwu E. ; Lee, Chung Len ; Shen, Wen Zen

Author_Institution

Inst. of Electron., Nat. Chiao Tung Univ., Hsin-Chu, Taiwan

fYear

1990

fDate

10-14 Sep 1990

Firstpage

809

Lastpage

814

Abstract

A study of fault collapsing for synchronous sequential circuits is presented. Two phenomena, self-hiding and delay-reconvergence, which invalidate the combinational fault dominance relationship in sequential circuits are identified. These phenomena are caused by the existence of feedback paths and storage elements in sequential circuits. From this analysis, a single-fault fault-collapsing procedure for synchronous irredundant sequential circuits is proposed to reduce the faults for which test has to be generated. This procedure can be applied not only to a nonscan mode circuit, but also to a full-scan and a partial-scan mode circuit by cutting the inputs and outputs of scannable D flip-flops as the primary outputs and inputs of the circuit, respectively. This procedure has been applied to collapse faults for the 31 benchmark sequential circuits, and a 57% reduction in the number of faults as compared with the total number of original faults has been obtained

Keywords

flip-flops; logic testing; sequential circuits; D flip-flops; benchmark; delay-reconvergence; feedback paths; full-scan; nonscan mode circuit; partial-scan; self-hiding; sequential logic circuits; single-fault fault-collapsing; synchronous sequential circuits; Benchmark testing; Circuit analysis; Circuit faults; Circuit testing; Combinational circuits; Delay; Flip-flops; Logic testing; Sequential analysis; Sequential circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1990. Proceedings., International

Conference_Location

Washington, DC

Print_ISBN

0-8186-9064-X

Type

conf

DOI

10.1109/TEST.1990.114098

Filename

114098