A BIST scheme using microprogram ROM for large capacity memories

Author

Koike, Hiroki ; Takeshima, Toshio ; Takada, Masahide

Author_Institution

NEC Corp., Kanagawa, Japan

fYear

1990

fDate

10-14 Sep 1990

Firstpage

815

Lastpage

822

Abstract

A practical microprogram ROM BIST (built-in self-test) scheme suitable for LSI memories is proposed. This BIST can be used to install N-pattern and N²-pattern test procedures, using BIST circuits with 12-word×10-b and 16-word×16-b ROMs, respectively. As a practical test procedure, a data retention test, in which BIST circuits with an 8-word×11-b ROM were used, was investigated. BIST circuit area overheads for the above three test patterns for 16-Mb DRAMs are less than 1%, 2%, and 1.5%, respectively. A testing method for the BIST circuits themselves, with no special BIST circuit overhead, is also proposed for more practical applications. The measured operational margin for a 16-Mb DRAM using the BIST showed a good agreement with that using an LSI tester

Keywords

DRAM chips; automatic testing; built-in self test; integrated circuit testing; integrated memory circuits; large scale integration; microprogramming; read-only storage; 10 bit; 11 bit; 120 bit; 16 Mbit; 16 bit; 256 bit; 88 bit; BIST; DRAM; IC testing; LSI; N-pattern; N²-pattern; automatic testing; built-in self-test; data retention test; large capacity memories; memory IC; microprogram ROM; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Fault detection; Laboratories; Large scale integration; Microelectronics; Read only memory; Read-write memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1990. Proceedings., International

Conference_Location

Washington, DC

Print_ISBN

0-8186-9064-X

Type

conf

DOI

10.1109/TEST.1990.114099

Filename

114099